Listening to Clock Jitter

I have tried to listen to clock jitter before but never succeeded in that, well until now!

Test setup: 12MHz clock derived either from external MEMS oscillator or from Lattice XO2 FPGA on-chip PLL generating 12MHz output from 12MHz reference input. The clock is feeding 8 bit shift register that is repeatedly sending out 8 bit pattern. Shift register output is driving FPGA IO pins, and those are connected via audio transformer to 600 ohm differential input of Focusrite USB Audio.

There is a push-button that selects between 12MHz from MEMS and from internal PLL.

Idle pattern 0x69 (..01101001..) low noise level is MEMS oscillator, switching to PLL clock add significant noise, that can take 2 discrete levels. This can only be if the "clock jitter" noise is also repeating with 8 (or some power of 2) clocks.

Idle patterns 0x55 (..01010101..) and 0x33 (..00110011..) did not show any noise difference between MEMS and PLL clock sources.

Interesting uh? Different silence pattern do exhibit so different output: 0x69 is sensitive to clock, while 0x55 and 0x33 are not. What about 0x0F ?

Pattern 0x0F creates much higher level tone than 0x69, and the discrete levels are now more similar to each other compared to the levels of 0x69 pattern.

This tone comes from 0x0F the frequency is about 3500 Hz.

So basically we have a signal chain like this

12MHz MEMS clock -> PLL -> 12MHz -> divide by 8 -> 3.5Khz tone! If we remove the PLL from the chain the tone is gone.

If the PLL makes such a clear tone out of 00001111 pattern, it should also have some impact on DSD audio as well?

Let's try, I start DSD audio data streaming from the PC to the same hardware setup (8 bit shift register..) and yes, the switch between MEMS clock and PLL clock clearly adds white noise when PLL clock is selected.

So confirmed - clock jitter does have impact on DSD audio quality. OK, yes the XO2 PLL clock must be indeed really bad in terms of "audio quality" but this experiment clearly shows that better clock gives better results.

I can now use this or similar setup to compare clock jitter from different sources.