The One Hour Bible

The One Hour Bible: Writing Sacred Form in the Age of AI

Blurb: In one hour on a Sunday afternoon, I wrote an entire “Bible” with the help of AI — not to imitate scripture, but to explore creativity, collaboration, and meaning in the age of machines.

Last Sunday, I set myself a creative challenge: could I write an entire Bible in one hour — not a rewrite or parody, but an entirely new text with structure, rhythm, and spiritual intent?

With the help of AI, I did. The finished work, The One Hour Bible, is now available on the GOLC (Grand Old Lady’s Contest) GitHub site.

The Experiment

This was never about replacing scripture or imitating sacred language. It was about exploring what human–AI collaboration can accomplish under extreme creative constraints. Could meaningful writing emerge when guided by human intent but composed through machine assistance?

I provided the concept, structure, and thematic focus — drawing on philosophical, poetic, and moral ideas — while AI contributed speed, pattern recognition, and a remarkable ability to sustain tone. Together, we shaped a text that feels ancient in rhythm yet modern in perspective.

The Process

Working within a strict sixty‑minute limit forced focus. Every choice — structure, vocabulary, pacing — had to serve the core themes: creation, doubt, purpose, and renewal. AI accelerated the drafting process, allowing me to treat it almost like a co‑editor rather than a simple writing tool.

Surprisingly, coherence didn’t suffer. In fact, constraints seemed to enhance it. The text evolved as a dialogue between human values and algorithmic logic — a kind of modern psalmody generated through code and consciousness.

Why It Matters

The One Hour Bible is not a religious text, but a creative artifact. It exists to spark discussion about authorship, creativity, and collaboration in the era of generative technology. How much of art lies in intention rather than execution? Can technology deepen, rather than dilute, inspiration?

I believe it can. Tools like AI can help us move faster through form — drafting, experimenting, rewriting — so we can spend more time reflecting on meaning.

Open Source Creativity

The project is fully open on GitHub. It’s meant to be read, questioned, expanded, or even remade. The open nature of the work reflects its purpose: to invite others into the creative conversation about what it means to make something sacred — or at least meaningful — in one hour.

Final Thoughts

This experiment taught me that technology doesn’t diminish creation; it reframes it. Speed doesn’t have to mean superficiality. Sometimes, urgency brings clarity.

Writing a Bible in one hour proved that intention and imagination still matter most — even when assisted by code.

Aniversity is open!

Yesterday I opened Aniversity, a new type of university for everyone.

Aniversity lives in GitHub.

The first 13 questions are published! Have fun!

Apple-1 on FPGA

 I started with electronics in 1979 at age of 14. And am doing it ever since. One chip I really wanted to use was MC6809. I was even able to buy it on the black market. But I have never worked with it. But look what I did see today:

I see the welcome screen of Replica-1 compatible computer running on MC6809 compatible IP Core. My first ever greeting from 6809! Makes me smile.

HOW? Easy, I did take the existing Replica-1 repo at github here and then adapted it for the FPGA board on my table. What was on my table? It was AXE5-Falcon PCB with serial number #0. There is some info about AXE5-Falcon here.

I spent about two hours to get it to work. Why so long? Because the usual suspect UART RXD and TXD. They are swapped at the level shifter. So I did not notice that at first, so I swapped RXD/TXD several times with no luck. And then I realized that the FTDI UART pins at FPGA are in 1.8V bank, I had selected 3.3! That was the mistake and real reason for two hours debug session.

So now it works.

But I have no idea what I can do with it :) there should be possible to enable ROM BASIC, I so assume. And with PMOD SD card adapter it could even access SD cards?

Well, it works :) so I can ask the author what I can do with it.

It it is named as Replica-1, but Replica-1 is replica of Apple-1 home computer. So I have a Apple-1 on my desk.

UPDATE: by changing two lines of code the processor is changed to 6502 and ROM to Basic+monitor, with a magic:

E000R

The Basic starts, and it is possible to enter and execute Basic programs.

How big is it? On the AXE5-Falcon board, the logic utilization is less than 1%. For 48Kbyte RAM and 8KB Basic ROM, the block RAM utilization is below 8%. So I could instantiate 10 Apple-1 computers in a single FPGA!

What about really small FPGA? Trying out special version for MAX1000 with 10M08 FPGA. And here is an adventure game starting:

Note for UART downloading, you need to use teraterm (and not putty) and set line end delay to 7ms then the download works.

FPGA Power Consumption

"Please give me  FPGA power consumption at maximum load"! This is not such an uncommon question. This is what FPGA SoM vendors hear all the time.

Answer? The direct answer is: cannot tell.

FPGA is a very complicated device that can burn a very different amount of power depending on the loaded design. Most FPGA's can be converted to an HEATER that generates lots of heat and burns lots of energy. So the "maximum load" does not make sense, maximum loaded FPGA makes no sense, except being a heater.

The good thing is that with a somewhat reasonable design, the FPGA consumes a reasonable amount of energy. How much? To answer this question, pretty much all FPGA vendors provide power estimator tools in some form. Some versions are Excel worksheets, some are power calculator apps. In both cases they provide an estimation how much power will be used. Important is to notice that the power consumption depends on the FPGA Die temperature. At higher temperatures, the idle current increases a lot. So it may be good to play with the temperature settings in the power estimator tool. The tool may have different names, be it XPE, PDM or PTC or something else.

So if you need to know how much current you must be ready to deliver to the FPGA SoM, run the power estimator first, then calculate the power losses in the onboard DCDC regulators, and you get some indication of how much current is needed.

Ballbark numbers? (For FPGA SoM's):

If you have a small FPGA (say 50KLE) running a soft processor core at 100MHz and some low-speed peripherals, chances are that you consume less than 1W total.

AMD Zynq-7 based SoM with small FPGA fabric and low load on the FPGA? Calculate with a minimum of 3W.

AMD MPSoC based SoM with small FPGA fabric and low load on the FPGA? Calculate with a minimum of 5W.

SoM power consumption depends on the FPGA power and power losses in the DCDC regulators. While DCDC regulators have decent efficiency, it is peaking usually at 75% of the max load. The power losses at low currents can be rather big. So, for example AXE5000 board consumes about 1.7W doing nothing, whereas Altera PTC tool says that the FPGA consumes 0.67W, so about 1W must be power losses. AXE5000 uses 5x times TDK's FS1606 DCDC converters that can deliver each up to 6A, those DCDC are not optimized for low loads and consume about 200mW each at very light loads. So there is no mystery where the power goes.

So you always need to calculate FPGA power consumption and DCDC power losses.

God may Exist!

 All my life I have been an atheist, never believing I could ever believe in God. But now I truly believe that God may exist. 

USB Blaster III

 Altera Quartus release 24.2 brings some surprising news. The installation includes DLL files with "blaster3" in the filename, so the USB Blaster III support is really in the distribution included. There has however been no public announcement yet. The real release of the UB3 is planned for Quartus version 24.3, so this is the time when it will be announced. 

UB3 is based on FTDI's FT4232H chip. For onboard solutions, FT2232H can also be used. A single RGB LED is used for status. Integration schematics will be made public. No license or fee is required; anyone can use the onboard UB3 solution.

As of today USB-Programmer2 von Trenz Electronic uses UB3 compatible circuitry. For some reason Quartus 24.2 still does not recognize this programmer without Arrow DLL's, so we all need to wait 24.3 release.

LiteX test on CR00103

This is a quick and dirty guide about the process of how I got Litex to work on CR00103 board.

I have to admit that I have not generated any LiteX SoC designs lately. But I had some known working projects, so to start I did take the top.v and mem init files from one of the old known working projects.

Creating a new Radiant project and selecting the device. Adding files. I am copying the VexRiscv_min file also in a local folder so it is easily found in the project. 

Creating PIN constraints. Done.

Well not yet there, the top.v I am using requires 100MHz clock, and I only have 12MHz on CR00103. So starting IP Wizard and generating PLL named mypll.

Changing the top verilog to use newly created wire clk100 and adding at the end:

    mypll __(.clki_i(clk ),

        .clkop_o(clk100 ));

Done. Does it work?

And indeed Litex is booting well. You can see how old the LiteX project is from January 2022.

Maybe I should give LiteX another try and regenerate directly from CR00103. I kind of did give up updating the LiteX board's support when many incompatible changes happened to LiteX. But I guess it is more stable now as a lot of time has passed.

Ah, let us publish the code, so others can experiment as well. Done, here:

https://github.com/micro-FPGA/CRUVI/tree/master/carriers/CR00103/test_litex