Fast-Serial, Part II

Taking the FPGA code for the fast-serial "echo" to Vivado did take, well no time!

The "RTL" block includes exactly the same code I used previously on Gowin and Lattice boards. I even left the "LED counter" port there with connection to VIO (Virtual I/O).

This is how the setup looks like XO2000 + TE0723

First attempt did return garbage and not correct echo, this is possible due to timing issues, I used now maximum serial interface clock of 50MHz. In the test with Gowin/Lattice I had clock of only 12MHz and did tweak the interface to work by using negative edge flip-flop. Now the path from FTDI to the "processing" FPGA (Zynq on TE0723) has additional not constrained delay introduced by the XO2 FPGA on XO2000 board. So for the functional test I am reducing the clock to around 12MHz - and now I have correct echo, same as it was with the same code on Gowin and Lattice boards.

Time to write the actual IP Core now!

First I add AXI-Stream ports to the "top" VHDL file I used previously as design top and then I add this as module to newly created Vivado BD and it looks then like this:

This is nice, I did not expect that Vivado would auto detect the AXI-Stream Interface, but it did and correctly too! As next step I create VHDL wrapper to be my Testbench toplevel file and add 7 lines of VHDL there. Testbench is ready!
Now the real work begins, after about 22 lines of VHDL code I am ready with "receive only" IP Core, time to simulate, does it work as expected? Yes it does, back to real life. I add ILA (Integrated Logic Analyzer) to the BD I used before, so it looks now like this:

Now a real test, sending "Hello World!" Core works and indeed it does.

This is ILA snapshot from "12345678901234567890" sent with putty. There is a thing that FT2232 datasheet does not tell you, it seems there is always 3 extra bits of IDLE between bytes received.

Next step? Adding transmit portion, testing it and then wrapping it into Vivado Catalog IP Core...