Xilinx PUDC_B behavior

 Xilinx has lots of datasheets and documents describing their products. Still, it is sometimes not possible to know how Xilinx devices work. An example is the PUDC_B pin. This pin controls the pre-configuration pullups on I/O pads. When driven low then pullups are enabled. In 7 series this pin is located in a normal IO bank. So how do we disable the pre-configuration pull-ups? We need to drive PUDC_B to high (using a pullup resistor), in order to do that we need to supply I/O voltage to the bank that includes the PUDC_B pin. But when that power supply ramps up then initially PUDC_B would sample low and enable all pullups? So there must be a short time when pull-ups are enabled regardless of the PUDC_B pin?

So what it is? Does PUDC_B=high (resistive pull-up) really guarantee that pre-configuration pull-ups are disabled? Need to test. Need a suitable FPGA board first.

TE0723 Zynq Arduino board has PUDC_B pin accessible for measurements. Attaching DSO probes to spare I/O and PUDC and VCCIO of the bank.

And what we see? The spare I/O pin does indeed get pulled up, reaching 0.9 volts then dropping back to 0 when PUDC_B voltage reaches about 1 volt. Sure 0.9 volts is not yet logic high, but it is also not anymore valid logic 0 either. So the conclusion is that PUDC_B does not fully disable configuration pullups as the input reference is at about 1 volt causing the internal pullups to be enabled during power-up for short time.

Here at Xilinx forums some DSO screenshots!