FPGA Power Supply measurements PART I

FPGA's are simple - the only problem is POWER supply design, if you do the power right chances are it is all good. But how to evaluate the power supply? Here is howto:

Start Vivado, new project, create some "power load" blocks and connect them VIO and then add XADC and add ILA, a work that takes maybe two hours from scratch.

Results? Here they are, the first test-victim was Digilent cmodA7 with Artix-A35T

XADC based scope view of VCCINT sampled with 1MSPS, load toggles with about 10KHz, and here is slow capture with Vivado XADC analyzer displaying valid voltage values:

We see 150mV ripple! The load step is about 300mA. Does not look good! What if I add more load? Surprisingly adding 2x more registers into the load chain did not make much difference, must be that routing changed to be more compact and total power efficiency increased.

But can we use this tool to compare different boards? I have one more A35T based board, so doing a quick recompile for the other board, here are the results - with exactly the same design!

Totally different picture, the load step is not at all visible, just not there.

Wau. This seems much better.
Makes me feel better as the second board is made by me - it is TE0711 SoM.

There load step does have influence on the VCCINT but it does not introduce any additional ripple to the DCDC output, guess what this ripple is because of LLM mode is enabled on TE0711 by default, can be disabled as option, then it would be more quieter at low loads.

Of course there is so much more power supply testing that is possible to-do, but even such a simple test can reveal major differences in the power supply.