RISCV SoftCPU Contest Part III

RISCV - Getting started with Zephyr

To my big surprise Zephyr provides build instruction for Windows users, this is really unexpected.

After lots of tweaking and a long evening on the next morning I am getting closer to compile something with zephyr targeting riscv architecture.

Blinky Example (blink a LED with GPIO), error for different target boards selected:

BOARD=m2gl025_miv - error gpio drivers are missing
BOARD= zedboard_pulpino - /core/isr.S:447 Error: unrecognized opcode 'eret'
BOARD=hifive1 - /core/fatal.c:198 undefined reference to 'cause_str'
BOARD=qemu_riscv32 - error gpio drivers are missing

So it seems that LED Blinky example is not running out of the box.

Hello World Example

BOARD=m2gl025_miv - OK, ROM: 10 Kbyte, RAM 4 Kbyte
BOARD= zedboard_pulpino - /core/isr.S:447 Error: unrecognized opcode 'eret'
BOARD=hifive1 - OK, ROM: 14 Kbyte, RAM 4 Kbyte
BOARD=qemu_riscv32 - OK, ROM: 1 Kbyte, RAM 13 Kbyte

Philosophers

BOARD=m2gl025_miv - OK, ROM: 18 Kbyte, RAM 9 Kbyte
BOARD=qemu_riscv32 - OK, ROM: 1 Kbyte, RAM 27 Kbyte

Synchronization 

BOARD=m2gl025_miv - OK, ROM: 11 Kbyte, RAM 6 Kbyte

BOARD=qemu_riscv32 - OK, ROM: 1 Kbyte, RAM 16 Kbyte

What is interesting is that ROM code for QEMU is always the same size 1052 Bytes long while for the real targets the ROM size is different. The reason for this are the linker files, the instructions are not always in ROM sections - so we can not use the default memory map statistics to see how large the instruction memory is.

What we do see is that 32K shared RAM space for instructions and data should be sufficient for all the RTOS examples that are needed to pass the requirements set by the contest rules.

Setting up compliance testing

Currently the mains stream RISCV Compliance suite is only providing "environment" for instruction set simulators. Forked repo https://github.com/micro-FPGA/riscv-compliance

provides some more environments, most notably "absmin" enviroment.

 

What is the best way to test the compliance of the SoftCPU ? Well the best way is that we design a new Instruction Set Simulaor that simulates our SoftCPU and that we validate our simulator first.

And here screenshot from this simulator passing compliance test suite for LW instruction (compiled with absmin environment).