LiteX test on CR00103

This is a quick and dirty guide about the process of how I got Litex to work on CR00103 board.

I have to admit that I have not generated any LiteX SoC designs lately. But I had some known working projects, so to start I did take the top.v and mem init files from one of the old known working projects.

Creating a new Radiant project and selecting the device. Adding files. I am copying the VexRiscv_min file also in a local folder so it is easily found in the project. 

Creating PIN constraints. Done.

Well not yet there, the top.v I am using requires 100MHz clock, and I only have 12MHz on CR00103. So starting IP Wizard and generating PLL named mypll.

Changing the top verilog to use newly created wire clk100 and adding at the end:

    mypll __(.clki_i(clk ),

        .clkop_o(clk100 ));

Done. Does it work?

And indeed Litex is booting well. You can see how old the LiteX project is from January 2022.

Maybe I should give LiteX another try and regenerate directly from CR00103. I kind of did give up updating the LiteX board's support when many incompatible changes happened to LiteX. But I guess it is more stable now as a lot of time has passed.

Ah, let us publish the code, so others can experiment as well. Done, here:

https://github.com/micro-FPGA/CRUVI/tree/master/carriers/CR00103/test_litex