Xilinx 3.3V LVDS

Sometimes we have a Xilinx 7 series FPGA board with 3.3V VCCIO (HR bank) and we need LVDS output in those banks. What to-do? Selecting LVDS for those banks will not work at all, because Xilinx 7 series IO drive circuits include a VCCIO comparator that switches the differential (except TMDS_33) outputs off if the VCCIO is above 2.65V.

Solution 1: We select LVCMOS33 and use complementary outputs in RTL code. This is a very rude approach, but it may in some rare cases be acceptable.

Solution 2: We use LVCMOS33 outputs with an external resistor divider network (3 resistors) to adjust the differential output voltage to LVDS levels.

Solution 3: We use TMDS_33 outputs with 50 ohms pull-up resistors to 1.5V. This is the best solution, but it needs external termination voltage.

Solution 4: We use TMDS_33 outputs with a 100ohm resistor divide option, one resistor from signal to ground, and one resistor from signal to 3.3V supply (4 resistors total). This should also be a somewhat acceptable solution.

Solution 5: We use external CMOS to LVDS buffer IC.

Differential inputs work at 3.3 VCCIO, only on-chip termination is not available, so you need an external 100ohm parallel termination resistor for inputs.

See also Xilinx answer record 43989