UHSA UART High Speed ASCII

 UHSA stands for UART High Speed ASCII protocol. The protocol is designed to be very low level to be able to tunnel binary data to multiple streams. The encoding is ASCII so it can always be entered from a regular terminal program. The protocol is very simple and can be handled by microcontroller or FPGA code directly.

I really haven't had time to ever publish the protocol, but it is internally used in several products. One of them is TEI0010 a small sensor demo board. It is still available from Arrow online shop.

If you want to use this board for USB to I2C bridge then you need to change IO location for two pins:

You possibly also need to change the IO standard to 3.3V LVCMOS. 

Python source code is also included in the download archive. 

The design if not modified allows I2C and SPI access to all onboard sensors and peripherals.

#

# ADPD register access functions

#

def ADPD_write_reg(reg, value, serialport):

    serialport.reset_input_buffer()          

    cmd = "<c8K%0.2xK%0.2xK%0.2xK>" % (reg, (value >> 8), (value & 0xFF))

    serialport.write(bytearray(cmd,'utf8'))   

def ADPD_read_reg(reg, serialport):

    serialport.reset_input_buffer()          

    cmd = "<c8K%0.2xK<c9K..m..M>" % reg       

    serialport.write(bytearray(cmd,'utf8'))   

    s = serialport.read(4)

    return int(s, 16)

The above is UHSA encoded commands to read write a 16-bit register over the I2C bus.

  

Xilinx PUDC_B behavior

 Xilinx has lots of datasheets and documents describing their products. Still, it is sometimes not possible to know how Xilinx devices work. An example is the PUDC_B pin. This pin controls the pre-configuration pullups on I/O pads. When driven low then pullups are enabled. In 7 series this pin is located in a normal IO bank. So how do we disable the pre-configuration pull-ups? We need to drive PUDC_B to high (using a pullup resistor), in order to do that we need to supply I/O voltage to the bank that includes the PUDC_B pin. But when that power supply ramps up then initially PUDC_B would sample low and enable all pullups? So there must be a short time when pull-ups are enabled regardless of the PUDC_B pin?

So what it is? Does PUDC_B=high (resistive pull-up) really guarantee that pre-configuration pull-ups are disabled? Need to test. Need a suitable FPGA board first.

TE0723 Zynq Arduino board has PUDC_B pin accessible for measurements. Attaching DSO probes to spare I/O and PUDC and VCCIO of the bank.

And what we see? The spare I/O pin does indeed get pulled up, reaching 0.9 volts then dropping back to 0 when PUDC_B voltage reaches about 1 volt. Sure 0.9 volts is not yet logic high, but it is also not anymore valid logic 0 either. So the conclusion is that PUDC_B does not fully disable configuration pullups as the input reference is at about 1 volt causing the internal pullups to be enabled during power-up for short time.

Here at Xilinx forums some DSO screenshots!

GOWIN LittleBee development board

This small board (SKU TEC0117) for GOWIN FPGA is available from Trenz Electronics webshop. The JTAG programmer is on board - it is just a simple standard FT2223H MPSSE JTAG (empty FTDI EEPROM).

Pre programmed demo design is from RISC-V competition, it should show the following on the UART Terminal (115200, 8N1):

Note: depending on the production batch the boards may be unprogrammed from the factory. Note: you do not need GOWIN tools license to use the gowin programmer.

With empty FTDI EEPROM you need to select the second UART assigned to the board.

TIP: the GOWIN boards are delivered with empty FTDI EEPROM so they will enumerate as two UART's - it is OK to disable VCP loading for the channel A, then you only see one COM port assigned to the board. 

Select D2XX for Channel A and click program.