FPGA Power Supply measurements PART I

FPGA's are simple - the only problem is POWER supply design, if you do the power right chances are it is all good. But how to evaluate the power supply? Here is howto:

Start Vivado, new project, create some "power load" blocks and connect them VIO and then add XADC and add ILA, a work that takes maybe two hours from scratch.

Results? Here they are, the first test-victim was Digilent cmodA7 with Artix-A35T

XADC based scope view of VCCINT sampled with 1MSPS, load toggles with about 10KHz, and here is slow capture with Vivado XADC analyzer displaying valid voltage values:

We see 150mV ripple! The load step is about 300mA. Does not look good! What if I add more load? Surprisingly adding 2x more registers into the load chain did not make much difference, must be that routing changed to be more compact and total power efficiency increased.

But can we use this tool to compare different boards? I have one more A35T based board, so doing a quick recompile for the other board, here are the results - with exactly the same design!

Totally different picture, the load step is not at all visible, just not there.

Wau. This seems much better.
Makes me feel better as the second board is made by me - it is TE0711 SoM.

There load step does have influence on the VCCINT but it does not introduce any additional ripple to the DCDC output, guess what this ripple is because of LLM mode is enabled on TE0711 by default, can be disabled as option, then it would be more quieter at low loads.

Of course there is so much more power supply testing that is possible to-do, but even such a simple test can reveal major differences in the power supply.

Installing Litex

Litex website says that timvideos litex-buildenv should be used by newcomers - but that web starts about installing debian packages, so it seems to be immediate dead end for Windows users.

Let's try the regular way:
python litex_setup.py init install

some github repos are pulled in, then error that python3 is not found comes..

starting migen install manually, something happening.. done without errors? good!

Idea lets copy python.exe to python3.exe and try again main install and see what happens?

no errors, does it mean it is installed??

aa there is document how to install litex on windows, but it requires Windows 10 and linux subsystem so it really is not working on Windows native?

Thats not good news. Litex seems to be written in python, and python runs everywhere so it should run on Windows too right? If I only want to add new platforms to litex then it should be possible?

trying setup.py again something happens and voila I  have a file named EGG about 30Mbyte large. What can I do with it? And how todo anything with litex? litex web says, run installer, then:

go to: boards/targets and execute target you want?

But what command should I enter to execute a target?

cd litex\boards\targets

python arty.py

erorr not finding risc-v compiler ? that's not so bad, as the compiler was not built so this error is kind of expected, but what if I want to build the hardware with no SoftCPU ?

25 minutes later, here comes full HOWTO litex on Windows:

1) make copy of python.exe to python3.exe
2) python litex_setup.py init install
3) python setup.py install
4) cd litex\boards\targets\

create a new target :)
create a famous DO.BAT with 2 lines:

set path=X:\Xilinx\Vivado\2019.1\bin\;%path%
python s7mini.py --cpu-type=None

And this does indeed run without error until bitstream - as you see I am trying to build for Kevin Hubbard's Spartan-7 mini board.

At least some bitfile did come out, of course I used wrong platform file, but at least now it is possible to start working and add new platforms to litex

all you need is proper DO.BAT

:)

All done huh? Adding new platform python file, changing the new platform and trying to build:

error: can not import s7mini from the EGG ?? What egg ?

So how to I get the new local file into the egg?
RTFM
python setup.py build

and the EGG is updated cooool!

almost there, both platform and target file are listed as part of EGG inside egg-info but when trying to build with new platform it still throws an error..

seems that getting litex to work in one day is not possible :(

not giving up yet, manual copy of the platform file to C:\python3\lib\site-packages seems to work as temporary workaround

... building for s7 minim done, programming FPGA, LED is ON

it works, the complete flow

and we have blinking LED as well..

and Vexriscv Litex BIOS starts as well, cool very cool..

NOTE: if you do not have the same toolchain installed you may have to patch in


C:\Python37\Lib\site-packages\litex-0.2.dev0-py3.7.egg\litex\soc\cores\cpu\vexriscv

file core.py:

#        return ("riscv64-unknown-elf", "riscv32-unknown-elf")
        return ("riscv-none-embed", "riscv-none-embed")

thats all folks!